1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically to an EEPROM (electrically erasable programmable ROM) provided with a plurality of batch erase blocks each composed of a plurality of nonvolatile memory cells erasable simultaneously.
2. Description of the Prior Art
A batch erase EEPROM by which the size of memory cells can be reduced has been developed. The batch erase type EEPROM can be classified into a chip erase type (all the memory cells in a semiconductor memory device are erased simultaneously) and a block erase type (the memory cell array is divided into a plurality of blocks and the memory cells are erased in the unit of block independently and simultaneously). The latter block erase type, in particular has such an advantage as to cope with written data of various volumes, there exists an expectation as the usage of substitute for a magnetic disk drive.
FIG. 1 shows a conventional block erase type EEPROM. The EEPROM includes a plurality of batch erase blocks 1000.sub.i (i=1 to n) composed of nonvolatile memory cells always erasable simultaneously, a plurality of row subdecoders 1001.sub.i (i=1 to n) provided for each batch erase block, for selecting cells to be read from among memory cells of each batch erase block 1000, a row main decoder 1002 for selecting one batch erase block from among the plural batch erase blocks 1000 on the basis of an internal address AI, and an address latch circuit 1003 for latching an external address AE input from the outside and generating an internal address AI. The row subdecoder 1001.sub.i functions as means for erasing the corresponding block.
In the configuration as described above, when the first batch erase block 1000.sub.1 and the second batch erase block 1000.sub.2 are required to be erased in the block erase operation for instance, the erase operation must be made in a predetermined sequence; that is, the batch erase block 1000.sub.1 is first erased by inputting a block address corresponding to the batch erase block 1000.sub.1 from the outside, and then the batch erase block 1000.sub.2 is erased by inputting a block address corresponding to the batch erase block 1000.sub.2 from the outside.
As described above, since the row main decoder 1002 can select only signal erase block at a time, it has been necessary to repeat the same erase operation when a plurality of batch erase blocks are required to be erased. Consequently, there exists a problem in that it takes a long time in order to erase a great number of batch erase blocks. For instance, when n-piece blocks are erased, if the time required for one erasure is 10 msec, n.times.10 msec is necessary. Therefore, in the conventional block erase type device, the erasure time increases with increasing number of the batch erase blocks to be erased. This problem is not involved in the chip batch erase type EEPROM.
As described above, in the conventional nonvolatile semiconductor memory device, there exists a problem in that the erasure time is long when a plurality of blocks are erased, as compared with the case where the all bits are erased simultaneously.
Furthermore, as an improved technique for erasing blocks effectively, a flash EEPROM system invented by Eliyshou HARARI et al. is disclosed in Japanese Patent Laid-open No. 2-292798 (Dec. 4, 1990) which corresponds to EPC-A2-398,895 published on Oct. 17, 1990.
In this system, a memory cell array is divided into sectors in the bit line direction in the unit of simultaneous erasure, and the simultaneous erasure is facilitated by selecting one or more sectors. In this system, however, since a select signal is simply applied to a decoder for selecting the sectors, there still exists a problem in that the total erasure time is not necessarily reduced.